1. Field
Exemplary embodiments of the present invention relate to a semiconductor device and a method of controlling the same, and more particularly, to a control of a write pipeline latch.
2. Description of the Related Art
In general, when a data strobe signal (DQS) is inputted from a system to a semiconductor device at an abnormal timing, the semiconductor device may be stuck due to a malfunction in a write operation. In this case, there is a concern in that the semiconductor device needs to be initialized for a normal operation.
FIG. 1 is a timing diagram in a write operation of a conventional semiconductor device.
Referring to FIG. 1, a semiconductor device including a data strobe signal (DQS) counter generates an internal write signal WR(WL-05) in response to a data strobe signal DQS that is received after column address strobe write latency (CL) from a point in time at which a write command WT is received.
If a system inputs the data strobe signal DQS to the semiconductor device at an abnormal timing, a malfunction may be generated in the write operation of the semiconductor device.
FIG. 2 is a timing diagram in a write operation of a conventional semiconductor device when a data strobe signal is received at an abnormal time point.
Referring to FIG. 2, if a system inputs a data strobe signal DQS at an abnormal timing , for example, before the CWL passes, a semiconductor device may not count the data strobe signal DQS appropriately because a data strobe input signal DQS_IN may not latch an internal write signal WR(WL-05).
For example, if a CWL value is set to ‘10’, it means that the number of clock cycles tCK) necessary for an external write command WT, the data strobe signal DQS, and data DQ to be received is ‘10’.
In order to inform the semiconductor device of the CWL value through a mode register set (MRS).
That is, the CWL value is set to ‘10’ and the semiconductor device is informed of the CWL value of ‘10’. However, when a memory controller sends a clock CLK, the clock CLK may be received to the semiconductor device in the ninth clock or the eleventh clock.
Such a case may be referred to as the CWL violation of a data strobe signal DQS.
Furthermore, a CWL value may be inevitably violated, in particular, in a training process of a semiconductor device.
That is, there is a possibility that a data strobe signal DQS is received to semiconductor device while failing to meet an agreed CWL value during a data training process, which is performed for finding an optimized timing of the data strobe signal DQS corresponding to the semiconductor device.
In such a case, there may be a concern in that the activation order of the write pipelines in the semiconductor device may malfunction.